Z
Zenpiya
DFT Lead
Bangalore, INSur siteCDITemps plein
Publié 5 oct. 2026
Cet emploi est publié en EN
Lead the overall DFT architecture, planning, implementation, and sign-off for complex SoC/ASIC designs.
Define and implement DFT strategies including:
Develop and optimize ATPG patterns and improve fault coverage.
Analyze and resolve DFT-related issues across RTL, synthesis, physical design, STA, and verification.
Work closely with RTL Design, Verification, Physical Design, STA, and Silicon Validation teams.
Perform DFT rule checks, coverage analysis, pattern validation, and debug.
Support DFT sign-off and ensure design readiness for tape-out.
Review DFT implementation and provide technical guidance to the team.
Mentor DFT engineers and establish best practices and methodologies.
Drive technical discussions with internal teams, customers, and external stakeholders.
Track project schedules, identify risks, and ensure timely delivery of DFT milestones.
Stay current with emerging DFT methodologies, tools, and semiconductor industry trends.
8+ years of hands-on experience in DFT, with proven technical leadership experience.
Strong understanding of DFT concepts and methodologies for ASIC/SoC designs.
Strong hands-on experience with Scan, ATPG, MBIST, JTAG/Boundary Scan, and test compression.
Experience with industry-standard DFT tools such as Synopsys TestMAX/TetraMAX, Siemens Tessent, Cadence Modus, or equivalent.
Good understanding of Verilog/SystemVerilog and RTL design flows.
Experience with DFT insertion, synthesis, ATPG generation, coverage analysis, and pattern validation.
Strong debugging and problem-solving skills.
Good understanding of ASIC/SoC design and verification flows.
Experience working across front-end and back-end design teams.
Strong communication, leadership, and team-management skills.
Define and implement DFT strategies including:
- Scan insertion and scan architecture
- ATPG
- MBIST/LBIST
- Boundary Scan/JTAG
- Compression
- Test modes and test points
- OCC/clock test structures
Develop and optimize ATPG patterns and improve fault coverage.
Analyze and resolve DFT-related issues across RTL, synthesis, physical design, STA, and verification.
Work closely with RTL Design, Verification, Physical Design, STA, and Silicon Validation teams.
Perform DFT rule checks, coverage analysis, pattern validation, and debug.
Support DFT sign-off and ensure design readiness for tape-out.
Review DFT implementation and provide technical guidance to the team.
Mentor DFT engineers and establish best practices and methodologies.
Drive technical discussions with internal teams, customers, and external stakeholders.
Track project schedules, identify risks, and ensure timely delivery of DFT milestones.
Stay current with emerging DFT methodologies, tools, and semiconductor industry trends.
Requirements
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.8+ years of hands-on experience in DFT, with proven technical leadership experience.
Strong understanding of DFT concepts and methodologies for ASIC/SoC designs.
Strong hands-on experience with Scan, ATPG, MBIST, JTAG/Boundary Scan, and test compression.
Experience with industry-standard DFT tools such as Synopsys TestMAX/TetraMAX, Siemens Tessent, Cadence Modus, or equivalent.
Good understanding of Verilog/SystemVerilog and RTL design flows.
Experience with DFT insertion, synthesis, ATPG generation, coverage analysis, and pattern validation.
Strong debugging and problem-solving skills.
Good understanding of ASIC/SoC design and verification flows.
Experience working across front-end and back-end design teams.
Strong communication, leadership, and team-management skills.
Aperçu du poste
Type de poste
Temps plein
Compétences requises
DFT architecture, planning, implementation, and sign-offScan insertion and scan architectureATPG development and optimizationMBIST/LBIST design and integrationBoundary Scan / JTAG implementationTest compression methodologiesTest modes, test points, and OCC/clock test structuresIndustry-standard DFT tools (e.g., Synopsys TestMAX/TetraMAX, Siemens Tessent, Cadence Modus)Verilog/SystemVerilog and RTL design flowsDFT insertion, synthesis, coverage analysis, and pattern validationDebugging DFT-related issues across RTL, synthesis, physical design, STA, and verificationLeadership, mentoring, and team management of DFT engineersCross-functional collaboration with RTL, Verification, Physical Design, STA, and Silicon Validation teamsProject execution, schedule tracking, and risk management for DFT milestones
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